View MACH120-12JC_3973428.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

final publication# 14129 rev: j amendment/ 0 issue date: november 1997 mach 1 & 2 families mach 1 & 2 families 1 com?: -12/15 ind: -18 mach120-12/15 high-performance ee cmos programmable logic distinctive characteristics u 68 pins in plcc u 48 macrocells u 12 ns t pd commercial, 18 ns t pd industrial u 77 mhz f cnt commercial u 48 i/os; 4 dedicated inputs; 4 dedicated inputs/clocks u 48 outputs u 48 flip-?ps; 4 clock choices u 4 ?alce26v12?blocks u speedlocking for guaranteed ?ed timing u pin-compatible with the mach221 general description t h e m a c h 1 2 0 i s a m e m b e r o f the high-performance ee cmos mach 1 f a m i l y . t h i s d e v i c e has approximately ?e times the logic macrocell capability of the popular palce22v10 without loss of speed. the mach120 consists of four pal blocks interconnected by a programmable switch matrix. the switch matrix connects the pal blocks to each other and to all input pins, providing a high degree of connectivity between the fully-connected pal blocks. this allows designs to be placed and routed ef?iently. the mach120 macrocell provides either registered or combinatorial outputs with programmable polarity. if a registered con?uration is chosen, the register can be con?ured as d-type or t-type to help reduce the number of product terms. the register type decision can be made by the designer or by the software. all macrocells can be connected to an i/o cell. if a buried macrocell is desired, the internal feedback path from the macrocell can be used, which frees up the i/o pin for use as an input. la t tice se m i con duc tor
mach120-12/15 3 mach 1 & 2 families block diagram 14129 j -1 i/o cells macrocells i/o 0 ?/o 11 12 12 52 x 54 and logic array and logic allocator oe i/o cells macrocells i/o 12 ?/o 23 12 12 52 x 54 and logic array and logic allocator oe 4 4 26 26 i 2 ? 3 i 6 ? 7 i/o cells macrocells i/o 36 ?/o 47 12 12 52 x 54 and logic array and logic allocator oe 26 i/o cells macrocells i/o 24 ?/o 35 12 12 52 x 54 and logic array and logic allocator oe 26 4 switch matrix clk 0 /i 0, clk 1 /i 1 , clk 2 /i 4 , clk 3 /i 5 4 block d block c bloc k a bloc k b
4 mach120-12/15 connection diagram top view plcc note: pin-compatible with the mach220 and mach221. pin designations clk/i = clock or input gnd = ground i = input i/o = input/output vcc = supply voltage 1 68 67 66 65 64 63 62 61 7 6 5 4 3 2 9 8 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 35 36 37 38 39 40 41 42 4329 30 31 32 33 3427 28 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 clk 0 /i 0 clk 1 /i 1 i 2 v cc gnd i 3 i/o 12 i/o 13 i/o 14 i/o 15 i/o 16 i/o 17 gnd i/o 18 i/o 19 i/o 20 i/o 21 i/o 22 i/o 23 v cc gnd i/o 24 i/o 25 i/o 26 i/o 27 i/o 28 i/o 29 gnd i/o 30 i/o 41 i/o 40 i/o 39 i/o 38 i/o 37 i/o 36 i 7 gnd v cc i 6 clk 3 /i 5 clk 2 /i 4 i/o 35 i/o 34 i/o 33 i/o 32 i/o 31 i/o 6 gnd i/o 5 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 gnd v cc i/o 47 i/o 46 i/o 45 i/o 44 i/o 43 i/o 42 gnd block a block d block b block c 14129 j -2
mach120-12/15 (com?) 5 mach 1 & 2 families ordering information commercial products v antis pr ogrammable logic products for commercial applications are available with several ordering options. the order number (v alid combination) is formed by a combination of: valid combinations the valid combinations table lists congurations planned to be supported in volume for this device. consult the local vantis sales ofce to conrm availability of specic valid combinations and to check on newly released combinations. family type mach = macr o array cmos high-speed mach 120 ?2 j c device number 120 = 48 macr ocells, 68 pins speed 12 = 12 ns t pd 15 = 15 ns t pd operating conditions c = commercial (0 c to +70 c) package type j = 68-pin plastic leaded chip carrier (pl 068) valid combinations mach120-12 jc mach120-15
6 mach120-18 (ind) ordering information industrial products v antis pr ogrammable logic products for industrial applications are available with several ordering options. the order number (valid combination) is formed by a combination of: valid combinations the valid combinations table lists congurations planned to be supported in volume for this device. consult the local vantis sales ofce to conrm availability of specic valid combinations and to check on newly released combinations. family type mach = macr o array cmos high-speed mach 120 ?8 j i device number 120 = 48 macr ocells, 68 pins speed 18 = 18 ns t pd operating conditions i = industrial (?0 c to +85 c) package type j = 68-pin plastic leaded chip carrier (pl 068) valid combinations mach120-18 ji
mach120-12/15 7 mach 1 & 2 families functional description the mach120 consists of four pal blocks connected by a switch matrix. there are 48 i/o pins and 4 dedicated input pins feeding the switch matrix. these signals are distributed to the four p al blocks for efcient design implementation. there are 4 clock pins that can also be used as dedicated inputs. the pal blocks each pal block in the mach120 (figure 1) contains a 48-product-term logic array, a logic allocator, 12 macrocells and 12 i/o cells. the switch matrix feeds each pal block with 26 inputs. this makes the pal block look effectively like an independent ?alce26v12? ther e are four additional output enable product terms in each pal block. for purposes of output enable, the 12 i/o cells are divided into 2 banks of 6 macrocells. each bank is allocated two of the output enable product terms. an asynchronous reset product term and an asynchronous preset product term are provided for ip- op initialization. all ip-ops within the pal block are initialized together. the switch matrix the mach120 switch matrix is fed by the inputs and feedback signals from the pal blocks. each p al block provides 12 internal feedback signals and 12 i/o feedback signals. the switch matrix distributes these signals back to the pal blocks in an efcient manner that also provides for high perfor mance. the design software automatically congures the switch matrix when tting a design into the device. the product-term array the mach120 product-term array consists of 48 product terms for logic use, and 6 special-purpose pr oduct terms. four of the special-purpose product terms provide programmable output enable, one pr ovides asynchronous reset, and one provides asynchronous preset. two of the output enable p roduct terms are used for the rst six i/o cells; the other two control the last six macrocells. the logic allocator the logic allocator in the mach120 takes the 48 logic product terms and allocates them to the 12 macrocells as needed. each macrocell can be driven by up to 12 product terms. the design softwar e automatically congures the logic allocator when tting the design into the device. table 1 illustrates which product term clusters are available to each macrocell within a pal block. refer to figure 1 for cluster and macrocell numbers. t able 1. logic allocation output macrocell available clusters output macrocell available clusters m 0 c 0 , c 1 m 6 c 5 , c 6 , c 7 m 1 c 0 , c 1 , c 2 m 7 c 6 , c 7 , c 8 m 2 c 1 , c 2 , c 3 m 8 c 7 , c 8 , c 9 m 3 c 2 , c 3 , c 4 m 9 c 8 , c 9 , c 10 m 4 c 3 , c 4 , c 5 m 10 c 9 , c 10 , c 11 m 5 c 4 , c 5 , c 6 m 11 c 10 , c 11
8 mach120-12/15 the macrocell the mach120 macrocells can be congured as either registered or combinatorial, with programmable polarity. the macrocell provides internal feedback whether congured as registered or combinatorial. the ip-ops can be congured as d-type or t-type, allowing for product-term optimization. the ip-ops can individually select one of four global clock pins, which are also available as logic inputs. the registers are clocked on the low-to-high transition of the clock signal. the ip- ops can also be asynchronously initialized with the common asynchronous reset and preset pr oduct terms. the i/o cell the i/o cell in the mach120 consists of a three-state output buffer. the three-state buffer can be congured in one of three ways: always enabled, always disabled, or controlled by a product ter m. if product term control is chosen, one of two product terms may be used to provide the contr ol. the two product terms that are available are common to six i/o cells. within each pal block, two product terms are available for selection by the rst six three-state outputs; two other pr oduct terms are available for selection by the last six three-state outputs. these choices make it possible to use the macrocell as an output, an input, a bidirectional pin, or a three-state output for use in driving a bus. speedlocking for guaranteed fixed timing the unique mach 1 architecture is designed for high performance? metric that is met in both raw speed, but even more importantly, guaranteed xed speed . using the design of the central switch matrix, the mach 120 product offers the speedlocking feature, which allows a stable xed pin-to-pin delay, independent of logic paths, routing resources and design rets for up to 16 product terms per output. other non-vantis cplds incur serious timing delays as product ter ms expand beyond their typical 4 or 5 product term limits. speed and speedlocking combine for continuous, high performance required in today's demanding designs
mach120-12/15 9 mach 1 & 2 families figure 1. mach120 pal block 0 4 8 12 16 20 24 28 4032 43 36 0 4 8 12 16 20 24 28 4032 43 36 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o switch matrix output enable output enable asynchronous reset asynchronous preset output enable output enable clk 12 i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell output macro cell output macro cell output macro cell output macro cell output macro cell output macro cell 12 output macro cell output macro cell output macro cell output macro cell output macro cell output macro cell 4 47 51 47 51 0 47 logic allocator c 0 c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 8 c 9 c 10 c 11 m 3 m 6 m 5 m 4 m 2 m 1 m 0 m 9 m 8 m 7 m 10 m 11 14129 j -3
10 mach120-12/15 (com?) absolute maximum ratings storage temperature . . . . . . . . . . . . . -65 c to +150 c ambient temperature with power applied . . . . . . . . . . . . . .-55 c to +125 c device junction temperature . . . . . . . . . . . . . +150 c supply voltage with respect to ground . . . . . . . . . . . . . . -0.5 v to +7.0 v dc input voltage . . . . . . . . . . . -0.5 v to v cc + 0.5 v dc output or i/o pin voltage . . . . . . . . . . . . . . . . . -0.5 v to v cc + 0.5 v static discharge voltage . . . . . . . . . . . . . . . . . 2001 v latchup current (t a = 0 c to 70 c) . . . . . . . . . . . . . . . . . . . . 200 ma str esses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum rat- ings for extended periods may affect device reliability. pro- gramming conditions may differ. operating ranges commercial (c) devices ambient temperature (t a ) operating in fr ee air . . . . . . . . . . . . . . . 0 c to +70 c supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . with respect to ground . . . . . . . . . +4.75 v to +5.25 v operating ranges dene those limits between which the func- tionality of the device is guaranteed. dc characteristics over commercial operating ranges notes: 1. these are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. i/o pin leakage is the worst case of i il and i ozl (or i ih and i ozh ). 3. not more than one output should be shorted at a time. duration of the short-circuit should not exceed one second. v out = 0.5 v has been chosen to avoid test problems caused by tester ground degradation. 4. measur ed with a 12-bit up/down counter pattern. this pattern is programmed in each pal block and capable of being loaded, enabled, and reset. parameter symbol parameter description test conditions min typ max unit v oh output high voltage i oh = -3.2 ma, v cc = min v in = v ih or v il 2.4 v v ol output low voltage i ol = 16 ma, v cc = min v in = v ih or v il 0.5 v v ih input high voltage guaranteed input logical high voltage for all inputs (note 1) 2.0 v v il input low voltage guaranteed input logical low voltage for all inputs (note 1) 0.8 v i ih input high current v in = 5.25 v, v cc = max (note 2) 10 m a i il input low current v in = 0 v, v cc = max (note 2) -10 m a i ozh off-state output leakage current high v out = 5.25 v, v cc = max v in = v ih or v il (note 2) 10 m a i ozl off-state output leakage current low v out = 0 v, v cc = max v in = v ih or v il (note 2) -10 m a i sc output short-circuit current v out = 0.5 v, v cc = max (note 3) -30 -130 ma i cc supply current (typical) v cc = 5 v, t a =25 c, f = 25 mhz (note 4) 85 ma
mach120-12/15 (com?) 11 mach 1 & 2 families capacitance (note 1) switching characteristics over commercial operating ranges (note 2) notes: 1. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modied where fr equency may be affected. 2. see switching test circuit, for test conditions. parameter symbol parameter description test conditions typ unit c in input capacitance v in = 2.0 v v cc = 5.0 v, t a = 25 c f = 1 mhz 6 pf c out output capacitance v out = 2.0 v 8 pf parameter symbol parameter description -12 -15 unitmin max min max t pd input, i/o, or feedback to combinatorial output 12 15 ns t s setup time from input, i/o, or feedback to clock d-type 7 10 ns t-type 8 11 ns t h hold time 0 0 ns t co clock to output 8 10 ns t wl clock width low 6 6 ns t wh high 6 6 ns f max maximum frequency (note 1) external feedback d-type 66.7 50 mhz t-type 62.5 47.6 mhz internal feedback (f cnt ) d-type 76.9 66.6 mhz t-type 71.4 55.5 mhz no feedback 83.3 83.3 mhz t ar asynchr onous reset to register ed output 16 20 ns t arw asynchr onous reset width (note 1) 12 15 ns t arr asynchr onous reset recovery time (note 1) 8 10 ns t ap asynchr onous preset to registered output 16 20 ns t apw asynchr onous preset width (note 1) 12 15 ns t apr asynchr onous preset recovery time (note 1) 8 10 ns t ea input, i/o, or feedback to output enable 12 15 ns t er input, i/o, or feedback to output disable 12 15 ns
12 mach120-18 (ind) absolute maximum ratings storage temperature . . . . . . . . . . . . . -65 c to +150 c ambient temperature with power applied . . . . . . . . . . . . . -55 c to +125 c device junction temperature . . . . . . . . . . . . . +150 c supply voltage with respect to ground . . . . . . . . . . . . . . -0.5 v to +7.0 v dc input voltage . . . . . . . . . . . . -0.5 v to v cc + 0.5 v dc output or i/o pin voltage . . . . . . . . . . . . . . . . . -0.5 v to v cc + 0.5 v static discharge voltage . . . . . . . . . . . . . . . . . 2001 v latchup current (t a = -40 c to +85 c) . . . . . . . . . . . . . . . . . . . 200 ma str esses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum rat- ings for extended periods may affect device reliability. pro- gramming conditions may differ. industrial operating ranges industrial (i) devices ambient temperature (t a ) operating in fr ee air . . . . . . . . . . . . . . -40 c to +85 c supply voltage (v cc ) with respect to ground . . . . . . . . . . . +4.5 v to +5.5 v operating ranges dene those limits between which the func- tionality of the device is guaranteed. dc characteristics over industrial operating ranges notes: 1. these are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. i/o pin leakage is the worst case of i il and i ozl (or i ih and i ozh ). 3. not more than one output should be shorted at a time. duration of the short-circuit should not exceed one second. v out = 0.5 v has been chosen to avoid test problems caused by tester ground degradation. 4. measur ed with a 12-bit up/down counter pattern. this pattern is programmed in each pal block and is capable of being loaded, enabled, and reset. p arameter symbol p arameter description test conditions min typ max unit v oh output high voltage i oh = -3.2 ma, v cc = min v in = v ih or v il 2.4 v v ol output low voltage i ol = 16 ma, v cc = min v in = v ih or v il 0.5 v v ih input high voltage guaranteed input logical high voltage for all inputs (note 1) 2.0 v v il input low voltage guaranteed input logical low voltage for all inputs (note 1) 0.8 v i ih input high current v in = 5.25 v, v cc = max (note 2) 10 m a i il input low current v in = 0 v, v cc = max (note 2) -10 m a i ozh off-state output leakage current high v out = 5.25 v, v cc = max v in = v ih or v il (note 2) 10 m a i ozl off-state output leakage current low v out = 0 v, v cc = max v in = v ih or v il (note 2) -10 m a i sc output short-circuit current v out = 0.5 v, v cc = max (note 3) -30 -130 ma i cc supply current (typical) v cc = 5 v, t a = 25 c, f = 25 mhz (note 4) 85 ma
mach120-18 (ind) 13 mach 1 & 2 families capacitance (note 1) switching characteristics over industrial operating ranges (note 2) notes: 1. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modied where capacitance may be affected. 2. see switching test circuit, for test conditions. 3. parameters measured with 24 outputs switching. parameter symbol parameter description test conditions typ unit c in input capacitance v in = 2.0 v v cc = 5.0 v, t a = 25 c f = 1 mhz 6 pf c out output capacitance v out = 2.0 v 8 pf parameter symbol parameter description -18 unitmin max t pd input, i/o, or feedback to combinatorial output (note 3) 18 ns t s setup time from input, i/o, or feedback d-type 12 ns t-type 13.5 ns t h hold time 0 ns t co clock to output (note 3) 12 ns t wl clock width low 7.5 ns t wh high 7.5 ns f max maximum frequency (note 1) exter nal feedback 1/(t s + t co ) d-type 40 mhz t-type 38 mhz internal feedback (f cnt ) d-type 53 mhz t-type 44 mhz no feedback 1/(t wl + t wh ) 66.5 mhz t ar asynchr onous reset to register ed output 24 ns t arw asynchr onous reset width (note 1) 18 ns t arr asynchr onous reset recovery time (note 1) 12 ns t ap asynchr onous preset to registered output 24 ns t apw asynchr onous preset width (note 1) 18 ns t apr asynchr onous preset recovery time (note 1) 12 ns t ea input, i/o, or feedback to output enable (note 3) 18 ns t er input, i/o, or feedback to output disable (note 3) 18 ns
14 mach120-12/15 typical current vs . voltage (i-v) characteristics v cc = 5.0 v, t a = 25 c i ol (ma) 80 60 40 20 ?0 ?0 ?0 ?0 ?.0 ?.8 ?.6 ?.4 ?.2 .2 .4 .6 .8 1.0 v ol (v) output, low 14129 i oh (ma) 25 ?5 ?0 ?5 ?00 ? ? ? 1 2 3 4 5 v oh (v) output, high ?25 ?50 14129 j -5 i i (ma) 20 ?0 ?0 ?0 ?0 ? ? 1 2 3 4 5 v i (v) input ?00 14129 j -6
mach120-12/15 15 mach 1 & 2 families typical i cc characteristics v cc = 5 v, t a = 25 c the selected ?ypical?pattern is a 12-bit up/down counter. this pattern is programmed in each pal block and is capable of being loaded, enabled, and reset. maximum frequency shown uses internal feedback and a d-type register. 150 125 100 75 50 25 0 0 10 20 30 40 50 60 70 i cc (ma) frequency (mhz) 14129 j -7
16 mach120-12/15 typical thermal characteristics measured at 25 c ambient. these parameters are not tested. plastic q jc considerations the data listed for plastic q jc are for reference only and are not recommended for use in calculating junction temperatures. the heat- ow paths in plastic-encapsulated devices are complex, making the q jc measurement relative to a specic location on the package surface. tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package. furthermore, q jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. therefore, the measurements can only be used in a similar environment. the thermal measurements are taken with components on a six-layer printed circuit board. switching waveforms notes: 1. v t = 1.5 v. 2. input pulse amplitude 0 v to 3.0 v. 3. input rise and fall times 2 ns? ns typical. parameter symbol parameter description typ unitplcc q jc thermal impedance, junction to case 13 c/w q ja thermal impedance, junction to ambient 37 c/w q jma thermal impedance, junction to ambient with air ow 200 lfpm air 33 c/w 400 lfpm air 30 c/w 600 lfpm air 28 c/w 800 lfpm air 25 c/w 14129 j -8 combinatorial output t pd input, i/o, or feedback combinatorial output v t v t 14129 j -9 registered output v t input, i/o, or feedback registered output t s t co v t t h v t clock 14129 j -10 clock width t wh clock t wl
mach120-12/15 17 mach 1 & 2 families switching waveforms notes: 1. v t = 1.5 v. 2. input pulse amplitude 0 v to 3.0 v. 3. input rise and fall times 2 ns? ns typical. v t v t t arw v t t ar input, i/o, or feedback registered output clock t arr 14129 j -11 asynchronous reset input, i/o, or feedback v t v t t apw v t t ap t apr registered output clock 14129 j -12 asynchronous preset 14129 j -13 output disable/enable v t v t outputs t er t ea v oh ?0.5 v v ol + 0.5 v input, i/o, or feedback
18 mach120-12/15 key to switching waveforms switching test circuit *switching several outputs simultaneously should be avoided for accurate measurement. speci cation s 1 c l commercial measured output valuer 1 r 2 t pd , t co closed 35 pf 300 w 390 w 1.5 v t ea z ? h: open z ? l: closed t er h ? z: open l ? z: closed 5 pf h ? z: v oh ?0.5 v l ? z: v ol + 0.5 v must be steady may change from h to l may change from l to h does not apply don? care, any change permitted will be steady will be changing from h to l will be changing from l to h changing, state unknown center line is high- impedance ?ff state waveform inputs outputs ks000010-pal 14129 j -14 c l output r 1 r 2 s 1 test point 5 v
mach120-12/15 19 mach 1 & 2 families f max parameters the parameter f max is the maximum clock rate at which the device is guaranteed to operate. be- cause the exibility inherent in programmable logic devices offers a choice of clocked ip-op designs, f max is specied for three types of synchronous designs. the rst type of design is a state machine with feedback signals sent off-chip. this external feedback could go back to the device inputs, or to a second device in a multi-chip state machine. the slowest path dening the period is the sum of the clock-to-output time and the input setup time for the exter- nal signals (t s + t co ). the reciprocal, f max , is the maximum frequency with external feedback or in conjunction with an equivalent speed device. this f max is designated ? max external. the second type of design is a single-chip state machine with internal feedback only. in this case, ip-op inputs are dened by the device inputs and ip-op outputs. under these condi- tions, the period is limited by the internal delay from the ip-op outputs through the internal feedback and logic to the ip-op inputs. this f max is designated ? max internal? a simple in- ter nal counter is a good example of this type of design; therefore, this parameter is sometimes called ? cnt . the third type of design is a simple data path application. in this case, input data is presented to the ip-op and clocked through; no feedback is employed. under these conditions, the pe- riod is limited by the sum of the data setup time and the data hold time (t s + t h ). however, a lower limit for the period of each f max type is the minimum clock period (t wh + t wl ). usually, this minimum clock period determines the period for the third f max , designated ? max no feed- back. for devices with input registers, one additional f max parameter is specied: f maxir . because this involves no feedback, it is calculated the same way as f max no feedback. the minimum period will be limited either by the sum of the setup and hold times (t sir + t hir ) or the sum of the clock widths (t wicl + t wich ). the clock widths are normally the limiting parameters, so that f maxir is speci ed as 1/(t wicl + t wich ). note that if both input and output registers are use in the same path, the overall frequency will be limited by t ics . all frequencies except f max internal are calculated from other measured ac parameters. f max internal is measured directly. logic register clk logic register clk t co t s t s t s f max internal (f cnt ) f max external 1/(t s + t co ) logic register clk f max no feedback; 1/(t s + t h ) or 1/(t wh + t wl ) (second chip) register logic clk f maxir ; 1/(t sir + t hir ) or 1/(t wicl + t wich ) t sir t hir
20 mach120-12/15 endurance characteristics the mach families are manufactured using vantis?advanced electrically erasable process. this technology uses an ee cell to replace the fuse link used in bipolar parts. as a result, the device can be erased and reprogrammed, a feature which allows 100% testing at the factory. endurance characteristics input/output equivalent schematics parameter symbol parameter description units test conditions t dr min pattern data retention time 10 years max storage temperature 20 years max operating temperature n max repr ogramming cycles 100 cycles normal programming conditions v cc esd protection 1 k w input v cc 100 k w preload circuitry feedback input i/o v cc v cc 100 k w 1 k w 14129 j -15
mach120-12/15 21 mach 1 & 2 families power-up reset the mach devices have been designed with the capability to reset during system power-up. following power-up, all ip-ops will be reset to low. the output state will depend on the logic polarity. this feature provides extra exibility to the designer and is especially valuable in sim- plifying state machine initialization. a timing diagram and parameter table are shown below. due to the synchronous operation of the power-up reset and the wide range of ways v cc can rise to its steady state, two conditions are required to insure a valid power-up reset. these conditions are: 1. the v cc rise must be monotonic. 2. following reset, the clock input must not be driven from low to high until all applicable input and feedback setup times are met. power-up reset waveform p arameter symbol p arameter descriptions max unit t pr power-up reset time 10 m s t s input or feedback setup t ime see switching characteristics t wl clock width low 14129 j -16 t pr t wl t s 4 v v cc power registered output clock

▲Up To Search▲

Price & Availability of MACH120-12JC

	To Download MACH120-12JC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .